A Programmable Vision Chip with High Speed Image Processing - Université de Bourgogne Accéder directement au contenu
Communication Dans Un Congrès Année : 2009

A Programmable Vision Chip with High Speed Image Processing


A high speed Analog VLSI Image acquisition and pre-processing system is described in this paper. A 64×64 pixel retina is used to extract the magnitude and direction of spatial gradients from images. So, the sensor implements some low-level image processing in a massively parallel strategy in each pixel of the sensor. Spatial gradients, various convolutions as Sobel filter or Laplacian are described and implemented on the circuit. The retina implements in a massively parallel way, at pixel level, some various treatments based on a four-quadrants multipliers architecture. Each pixel includes a photodiode, an amplifier, two storage capacitors and an analog arithmetic unit. A maximal output frame rate of about 10000 frames per second with only image acquisition and 2000 to 5000 frames per second with image processing is achieved in a 0.35 μm standard CMOS process. The retina provides address-event coded output on three asynchronous buses, one output is dedicated to the gradient and both other to the pixel values. A prototype based on this principle, has been designed. Simulation results from Mentor GraphicsTMsoftware and AustriaMicrosystem Design kit are presented.
Fichier principal
Vignette du fichier
ichsip2008.pdf (1.14 Mo) Télécharger le fichier
Origine : Fichiers produits par l'(les) auteur(s)

Dates et versions

hal-00785915 , version 1 (07-02-2013)



Jérôme Dubois, Michel Paindavoine, Dominique Ginhac. A Programmable Vision Chip with High Speed Image Processing. 28th International Congress on High-Speed Imaging and Photonics (ICHSIP), Nov 2008, Camberra, Australia. pp.1-10, ⟨10.1117/12.822294⟩. ⟨hal-00785915⟩
190 Consultations
258 Téléchargements



Gmail Facebook Twitter LinkedIn More